This invention relates to a device and method for optimizing a program by invalidating an instruction of which execution is unnecessary in the program.
Conventionally, as disclosed in, for examples, Laid Open unexamined Japanese Patent Application Nos. 4-17031 and 3-132828 (corresponding to U.S. patent application, Ser. No. 421,866), the execution speed of a program is enhanced by deleting an unnecessary instruction in the program.
Especially, in a program in which plural assembler instructions are arranged, the optimization for reducing the time required for program execution is attained to some extent by deleting an instruction of which execution is unnecessary in the program. FIG. 5 shows a conventional example of a program in which the optimization by deleting the unnecessary instruction is practicable.
In the figure, reference numerals 401 and 402 denote same instructions successively appearing in a program. In this case, the internal state of a computer, i.e. the state of register or memory, is not changed between after execution of the first instruction 401 and after execution of the second instruction 402. Wherein, MOV instruction in the figure means an instruction for transferring a data between memories, between registers or between memory and register. DST denotes a destination which receives the data transmitted and SRC denotes a source which transmits the data. In this case, since the two same data transfer instructions are successive, one of the two instructions 401 or 402 is meaningless, which means one of the instructions 401 or 402 can be deleted.
Reference numerals 403 and 404 denote two different instructions in the program. In this case, the prior instruction 403 becomes meaningless by execution of the following instruction 404. Wherein SET means to set, CLR means to clear and FLAG denotes a flag. The flag is set according to the prior instruction 403, then the flag is immediately cleared by the following instruction 404. The flag setting has no meaning, thus the first instruction 403 can be deleted.
Reference numerals 405-408 denote instructions each for executing a given operation in numeric operation in the program. In FIG. 5, ADD means addition, SUB means subtraction, MUL means multiplication and DIV means division. The instruction 405 is an instruction for adding 0. The instruction 406 is an instruction for subtracting 0. The instruction 407 is an instruction for multiplying 1. The instruction 408 is an instruction for dividing by 1. No numerical values to be processed are changed by the execution of any of the instructions 405-408, thus the instructions 405-408 are unnecessary. Accordingly, the program is optimized by deleting the instructions 405-408.
As mentioned above, in the conventional optimization, the judgement is performed in view of the arrangement of the instructions or the instructions themselves in the program.
However, in such a conventional optimization, the program composed of instructions 201-204 arranged as in FIG. 3 cannot be optimized. In FIG. 3, MOV instructions are for data transfer between memories, between registers or between memory and register. REG at the instruction 201 denotes a 2-byte (=16-bit) register, REG.sub.-- H denotes an upper 1-byte part of the register and REG.sub.-- L denotes a lower 1-byte part thereof. 0.times.1000 means 1000 in hexadecimal numeral. According to the instruction 202, 0.times.1000 is transmitted to the register REG, namely, 0.times.10 and 0.times.00 are transmitted respectively to the upper and lower parts REG.sub.-- H, REG.sub.-- L substantially. Then, according to the instructions 203 and 204, 0.times.10 are transmitted to the upper and lower parts REG.sub.-- H, REG.sub.-- L respectively. Consequently, the transmission of 0.times.10 to the upper part REG.sub.-- H is repeated by the instructions 202 and 203, which means no substantial influence by deletion of the instruction 203.
However, since the conventional optimization is performed in view of only the arrangement of or the meaning of the instructions, the presence of repeated instruction cannot be detected in the program including the instruction which changes the internal state of the computer at any time, such as value of the register. Therefore, the optimization cannot be performed.